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hi there. anyone down to talk about silicon production (analog chips) in older processes? i'm talking to a fab and they're telling me the kind of design that i am talking to them about could result in a bunch of crosstalk, so i'm looking for ideas on how to mitigate that. the chip carries analog audio, so this is about capacitive coupling.

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hi there. anyone down to talk about silicon production (analog chips) in older processes? i'm talking to a fab and they're telling me the kind of design that i am talking to them about could result in a bunch of crosstalk, so i'm looking for ideas on how to mitigate that. the chip carries analog audio, so this is about capacitive coupling.

I would just do a tapeout with Tiny Tapeout and see if it matches expectations

tiny tapeout is great, but my ultimate goal is to go into commercial production with a fab

1:02 a.m.

however, i resolved the crosstalk issue. i guess it was a translation problem between russian and english.

1:02 a.m.

they didn't mean to say it was going to create a bunch of crosstalk, they were telling me they had a solution which has low cross talk.

1:02 a.m.

they just didn't know how to say it

So I'm trying to work on the power gates for TT but hitting some DRC errors. In particular NP.12 I don't understand.

4:15 p.m.

NP.12 : Overlap with P-channel poly2 gate extension is forbidden within 0.32um of P-channel gate. Which I understand as, "NPlus can't overlap poly that's used by a pmos if that poly is closer than 0.32um to the actual gate zone"

4:16 p.m.

But then I get this from the DRC. ( Only COMP / Nplus / Poly shown ). And the Nplus doesn't overlat Poly at all ...

bailey started a thread. 2025-11-25 2:45 a.m.